With emerging of the 3rd-generation (3G) mobile communication and other advanced digital mobile communication technologies, the number of Femtocell is increasing to meet the requirement. Time synchronization with high accuracy is required for the Femtocell. In general, a clock recovery module is included in a network terminal. Therefore, clock synchronization (i.e., frequency synchronization) is easily to be provided for the Femtocell. However, time synchronization is very difficult to be provided. Some technical issues need to be solved. FIG. 1 is a schematic diagram showing a scheme for achieving accurate time synchronization proposed in the art. Assuming that Offset is an offset between a slave clock and a master clock, Delay1 is a propagation delay from the master clock to the slave clock and Delay2 is a propagation delay from the slave clock to the master clock. Then the following may be known from FIG. 1 that:Ts0=Tm1+OffsetTs1−Ts0=Delay1
then, Offset=Ts1−Tm1−Delay1
similarly, Tm2=Ts2−Offset+Delay2
so, Offset=Ts2−Tm2+Delay2
If the delay from the master clock to the slave clock is equal to the delay from the slave clock to the master clock, i.e., Delay1=Delay2, thenOffset=(Ts1+Ts2−Tm1−Tm2)/2.  (1)
In this way, the offset between the slave clock and the master clock is obtained so that the slave clock can be synchronized with the master clock accurately.
However, in the case that an xDigital Subscriber Line (xDSL) device works for mobile backhaul, the Master corresponds to a central office (CO) equipment, and the Slave corresponds to a customer premises equipment (CPE). The channel between the CO equipment and the CPE is complicated, and passes through an analog circuit of the CO equipment, a cable, an analog circuit of the CPE and also digital signal processing circuits at the CO equipment and the CPE. As a result, a downlink delay from the CO equipment to the CPE may not necessarily be equal to an uplink delay from the CPE to the CO equipment; i.e., generally, Delay1≠Delay2. According to some measuring results, the difference between Delay1 and Delay2 is more than 1 μs. Therefore, the offset between the CO clock and the CPE clock cannot be derived directly with formula (1).
As shown in FIG. 2, a downstream delay includes a delay Δt1 of a CO digital transmitting circuit 70, a delay Δt2 of a CO analog transmitting circuit 203, a downstream delay Δt3 of a twisted pair 90, a delay Δt2′ of a CPE analog receiving circuit 205, and a delay Δt1′ of a CPE digital receiving circuit 80; and a upstream delay includes a delay Δt4 of a CO digital receiving circuit 75, a delay Δt5 of a CO analog receiving circuit 2005, an upstream delay Δt6 of a twisted pair 90, a delay Δt5′ of a CPE analog transmitting circuit 2003, and a delay Δt4′ of a CPE digital transmitting circuit 85. In general, Delay1=Δt1+Δt2+Δt3+Δt2′+Δt1′≠Delay2=Δt4+Δt5+Δt6+Δt5′+Δt4′, and the difference between the two delays is generally larger than 1 μs.
An xDSL receiver detects a frame boundary and implements frame synchronization during the initialization. In actual cases, a little error may exist with the synchronization algorithm, and the precision of the synchronization is restricted by the sampling rate and an error of the frame synchronization may affect the accuracy of the time synchronization. If the beginning of a specified frame is recorded as a time stamp Tm1 (at the CO side) or a time stamp Ts2 (at the CPE side) by a transmitter, an error is introduced when a time stamp Ts1 (at the CPE side) or a time stamp Tm2 is recorded by a receiver with an algorithm for frame synchronization. Due to the error of frame synchronization, an error introduced by recording the Ts1 at the CPE side or the Tm2 at the CO side will be very large. In particular, the error will be even larger when the Tm2 is recorded by the CO in the upstream direction with low sampling rate.
Delay1 may also be obtained by directly measuring a downstream channel delay. In this way, an offset between the CO and the CPE can be directly obtained, i.e., Offset=Ts1−Tm1−Delay1. However, at present, the measurement of the xDSL channel delay (especially the twisted pair) is not accurate enough, particularly when loop length is too long, large noises exist in the loop, or bridging taps exist in the loop.